1. Field of Invention
The present invention relates to computer system operation, including data transfer operations among the elements of a memory system that include data compression and decompression.
2. Description of Related Art
In some computer systems, including multicore processors systems and graphical processor systems, memory is organized hierarchically. The memory hierarchy can include a relatively small first level (L1) cache memory and a larger second level (L2) cache memory on the same integrated circuit as the processor core circuitry, along with off-chip, large scale memory implemented often using dynamic random access memory. In some configurations, a third level (L3) cache can be included on-chip. Other memory can be used for sharing data among processor cores, such as shared cache memory and message-passing memory. Additional memory in the hierarchy can include persistent stores, such as flash memory, magnetic disk drive memory, network-attached storage and so on. Given the variety of memory technologies, the organization of memory systems is very diverse.
As processor performance has improved, processors are executing programs over larger and larger data sets. Also, one processor or group of processors may concurrently execute many programs, each of which requires access to different sizes and types of data sets. For example, broad varieties of application programs acquire, collect, process, and display numerical data. Numerical data includes a variety of data types, such as integers, floating-point numbers, image data, video data, and graphics objects. Numerical data can be accumulated in large files, or acquired at high speeds, and movement of such data among elements of processor system memory hierarchies can cause bottlenecks in system performance.
Thus, the amount of memory available, in terms of the number of bytes, at each element of a memory system for a given computer system, and the bandwidth of the data channels among the elements of the memory system, can limit the efficiency and speed with which a given program can be executed. Given the variant computer systems architectures and variant memory system configurations, the control of data flow among the memory elements is often implemented in a platform-specific manner. This platform-specific memory management interferes with users' ability to individually manage data flow to improve the efficiency of the utilization of memory resources in a give computer system.
It is desirable to provide technologies that can be employed to improve efficiency of memory system operations in computer systems.
Commonly owned patents and applications describe a variety of compression techniques applicable to fixed-point, or integer, representations of numerical data or signal samples. These include U.S. Pat. No. 5,839,100 (the '100 patent), entitled “Lossless and loss-limited Compression of Sampled Data Signals” by Wegener, issued Nov. 17, 1998, and the U.S. patent application Ser. No. 12/605,245 (the '245 application), entitled “Block Floating Point Compression of Signal Data,” publication number 2011-0099295, published Apr. 28, 2011. The commonly owned patent application Ser. No. 12/891,312 (the '312 application), entitled “Enhanced Multi-processor Waveform Data Exchange Using Compression and Decompression,” by Wegener, publication number 2011-0078222, published Mar. 31, 2011, incorporated herein by reference, describes configurable compression and decompression for fixed-point or floating-point data types in computing systems having multi-core processors. In a multi-core processing environment, input, intermediate, and output waveform data are often exchanged among cores and between cores and memory devices. The '312 application describes a configurable compressor/decompressor at each core that can compress/decompress integer or floating-point waveform data. The '312 application describes configurable compression/decompression at the memory controller to compress/decompress integer or floating-point waveform data for transfer to/from off-chip memory in compressed packets. The commonly owned non-provisional patent application Ser. No. 13/534,330 (the '330 application), filed Jun. 27, 2012, entitled “Computationally Efficient Compression of Floating-Point Data,” incorporated herein by reference, describes several embodiments for compression floating-point data by processing the exponent values and the mantissa values of the floating-point format. The commonly owned non-provisional patent application Ser. No. 13/358,511 (the '511 application), filed Jan. 25, 2012, entitled “Raw Format Image Data Processing,” incorporated herein by reference, describes compression of raw format image data at least as fast as the image data rate.
In order to better meet the requirements of higher speed data transfer, reduced memory utilization and minimal computation in many computing applications, a need exists for computationally efficient compression and decompression in a DMA controller and corresponding DMA descriptors.